1. Field of the Invention
This invention relates to a parallel data transfer circuit which transfers parallel data from a transfer source circuit to a transfer destination circuit in a digital communication apparatus or a like apparatus.
2. Description of the Related Art
Various parallel data transfer circuits are conventionally known, and an exemplary one of conventional parallel data transfer circuits is shown in FIG. 2. Referring to FIG. 2, in the parallel data transfer circuit shown, parallel data are transferred from a data transfer source circuit 201 to a data transfer destination circuit 202. In order to allow the data transfer source circuit 201 to perform data storage address control of the data transfer destination circuit 202, an address signal 211, an upper byte write signal 212 and a lower byte write signal 213 are sent from the data transfer source circuit 201 to the data transfer destination circuit 202 before parallel data are transferred from the data transfer source circuit 201 to the data transfer destination circuit 202. For transfer of parallel data which include word data of 16 bits and byte data of 8 bits in a mixed condition, it is necessary to prepare a data bus of a word width and provide a change-over circuit such as an upper byte data selector 203 and a lower byte data selector 204 between the data transfer source circuit 201 and the data transfer destination circuit 202 so that an upper byte and a lower byte of the parallel data may be selected. Such changing over is controlled by the data transfer source circuit 201 (refer to, for example, Japanese Patent Laid-Open Application No. Showa 62-32748, No. Showa 62-49735 or No. Heisei 1-238338).
The parallel data transfer circuit further includes a data bus 214 for 8 bits between the data transfer source circuit 201 and the upper byte data selector 203, another data bus 215 between the data transfer source circuit 201 and the lower byte data selector 204, an upper byte data select signal line 216, a lower byte data select signal line 217, a further data bus 218 for 8 bits between the upper byte data selector 203 and the data transfer destination circuit 202, and a still further data bus 219 between the lower byte data selector 204 and the data transfer destination circuit 202.
The conventional parallel data transfer circuit described above is disadvantageous in that processing at the data transfer source circuit 201 is complicated and much time is required for transfer since the data transfer source circuit 201 performs changing over between the upper byte data selector 203 and the lower byte data selector 204 and controls the data storage address of the data transfer destination circuit 202 to transfer data.
Further, the conventional parallel data transfer circuit is also disadvantageous in that, when data are transferred without involving such changing over between data buses, a discontinuous empty portion is produced in the data storage area of the data transfer destination circuit 202 and consequently the data storage area cannot be used effectively.